The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-227578 filed on Aug. 11, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a timing signal occurrence circuit for adjusting delay of a timing signal, and targets, for example, delay adjustment of the timing signal in a semiconductor integrated circuit.
2. Related Background Art
A semiconductor circuit generally performs various processes by synchronizing each signal inputted with a clock. Therefore, there is no particular problem when using only a static circuit. However, when using a precharge circuit in order to improve speed, timings of the precharge period and the following evaluation period are out of synch. Because of this, an inherent timing signal for timing adjustment is necessary.
As one of timing signal occurrence circuits for generating such a timing signal, as shown in FIG. 1, a circuit for adjusting delay by using an inverter chain 51 is known. As shown in the timing diagram of FIG. 2, a circuit of FIG. 1 adjusts delay time by changing over the number of connection stages of the inverters.
Furthermore, as an example of the other timing signal occurrence circuit, when a circuit A needs timing when output of the other circuit B is settled, there may be provided with a dummy circuit which has the same delay time as a critical pass of the circuit A and generates the timing signal.
In case of providing the above-mentioned timing signal occurrence circuit in a semiconductor chip, a circuit is formed in combination with transistors. However, the higher a voltage applied to a transistor logic circuit constituted by combining with transistors is, and the lower the temperature is, the more quickly its circuit acts. When adjusting delay time by changing over the number of stages of the above-mentioned inverter chain 51, the delay time changes by voltage property and temperature property of the transistors.
Furthermore, when the dummy circuit is consisted of the inverter chain 51 or logic gate chain, a subject circuit (delay subject circuit) that the dummy circuit imitates is constituted alike by using the transistors, voltage property and temperature property of the transistors is cancelled to each other. Because of this, there is no particular problem.
On the other hand, when delay cause of the delay subject circuit is mainly a wiring delay (RC delay), the delay time due to the wiring delay does not change less than that due to the transistors, even if voltage or temperature changes. Because of this, a difference between the delay amounts of the dummy circuit and that of the delay subject circuit occurs. Accordingly, even if adjusting the number of connection stages of the inverters in the dummy circuit as the delay coincides with a certain condition, when voltage or temperature changes, according to circumstances, the delay time of the dummy circuit becomes shorter than the delay time of the delay subject circuit, and what is called as xe2x80x9cracingxe2x80x9d of the signal occurs.
The racing of the signal may also occur in accordance with process condition in case of forming the transistor, besides voltage and temperature. Because of this, when generating the timing signal by the inverter chain 51, if delay cause of the delay subject circuit is mainly wiring delay, it is necessary to take much margin for timing.
On the other hand, when generating the dummy circuit based on the critical path of the delay subject circuit and using output of the dummy circuit as the timing signal, the delay subject circuit delays at the same tendency as the dummy circuit. Because of this, there is high likelihood that its dummy circuit acts more stably than the dummy circuit is formed by using the inverter chain 51. However, because the dummy circuit imitates the critical path as it is, it is difficult to intentionally adjust the delay.
FIG. 3 is a block diagram of the timing signal occurrence circuit for adjusting timing between the timing that the operands are available on an operand bus and the timing that the calculator should start calculation. The circuit of FIG. 3 has a plurality of tristate buffers 1a, 1b and 1c connected to a delay clock line L1, a plurality of tristate buffers 2a, 2b and 2c connected to the operand bus L2, a plurality of calculators 3a, 3b and 3c connected to the input terminal of each of the tristate buffers 2a, 2b and 2c, and a calculator 3d for fetching the operands on the operand bus L2 and performing calculation by using the operands.
Among a plurality of tristate buffers 1a, 1b and 1c connected to the delay clock line L1, the left end tristate buffers 1a outputs a clock signal, and outputs of the other tristate buffers 1b and 1c is always high impedance state. That is, the tristate buffers beside the left end one is a dummy circuit to give a dummy load.
In case of a circuit of FIG. 3, the number of stages of the tristate buffers of the delay clock line L1 is set in accordance with the delay time of the critical path of the delay subject circuit. Because of this, it is difficult to intentionally adjust the delay time of the delay clock.
Furthermore, in case of the timing signal occurrence circuit for controlling the operational timing of a sense amplifier in a memory, the memory is provided with the sense amplifiers in accordance with the number of data bits. Because of this, the output of the timing signal occurrence circuit has to be distributed to each of the sense amplifiers via the buffer. Because of this, the signal delays for period necessary to path the buffers.
An object of the present invention is to provide a timing signal occurrence circuit capable of precisely adjusting timing without complicating a circuit.
In order to achieve the foregoing object, a timing signal occurrence circuit, comprising:
a plurality of signal output circuits configured to output a timing signal, and
a selecting circuit configured to select either one of the signal output circuits,
wherein output terminals of all of the signal output circuits are connected to a common timing signal line, and
wherein output terminals of the signal output circuits unselected by the selecting circuit.
Furthermore, a timing signal selecting circuit, comprising:
a plurality of memory cells connected to word lines and bit lines;
a plurality of dummy circuits connected to the word line an the bit line different from each other, and
a sense amplifier configured to amplify data read out from the selected memory cell,
wherein driving timing of the sense amplifier is controlled based on signal propagation time of each of the dummy circuits.
A simplest example of the timing signal selecting circuit is a circuit that fixes an enable input terminal of each output circuit of the timing signal to low level or high level. Or the timing signal selecting circuit is a register of holding the select value, output of which is connected to an enable input terminal of each timing output circuit.
According to the present invention, delay of the timing signal is adjusted by selecting either of a plurality of signal output circuits connected to a timing signal line. Because of this, it is possible to adjust timing easily and precisely.
Especially, by using the dummy circuit provided conventionally to provide a dummy load as a signal output circuit, it is possible to perform fine adjustment without adding new components, thereby curbing cost increase.
Furthermore, according to the present invention, because the signal output circuit is selected based on a critical path of a subject circuit, it is possible to adjust the delay of the timing signal so that the subject circuit acts normally.
Furthermore, according to the present invention, because the delay of the timing signal is adjusted so that the calculator fetches the operands after the operand on the operand bus has settled, it is possible to settle operation of the calculator.
Furthermore, according to the present invention, because it is possible to adjust the delay of the timing signal only by adjusting a control terminal of the tristate buffer, circuit configuration is simplified.
Furthermore, according to the present invention, because a selecting control circuit controls the select circuit, it is possible to programmably change over the delay adjustment of the timing signal.
Furthermore, according to the present invention, because operational timing of the sense amplifier is controlled by a plurality of dummy circuits provided in the memory array, it is possible to drive the sense amplifier at optimum timing.